FIG. 1 illustrates a conventional backside illuminated (“BSI”) image sensor 100 including pixel circuitry 101 and peripheral circuitry 102. Pixel circuitry 101 includes a photodiode (“PD”) region 105 disposed within a silicon P type epitaxial (“epi”) layer 110. Transistor pixel circuitry is at least partially formed in or on a P well 115. For the sake of clarity and so as not to clutter the drawings, only the transfer transistor (T1) and reset transistor (T2) of pixel circuitry 101 are illustrated. A first metal layer M1 for coupling to the gates of the transfer and reset transistors is disposed within an inter-layer dielectric layer 120.
Peripheral circuitry 102 is also disposed in or on epi layer 110, and may function as control circuitry, readout circuitry, logic circuitry, dark current reference cells, or the like. Peripheral circuitry is defined as any complementary metal-oxide semiconductor (CMOS) device that is not part of pixel circuitry 101. In FIG. 1, pixel circuitry 101 is illustrated to be immediately adjacent to peripheral circuitry 102; however, pixel circuitry 101 and peripheral circuit 102 may be separated by shallow trench isolations (STI) and/or a doped wells within epi layer 110, which isolate the pixel array from the rest of image sensor 100.
BSI image sensor 100 is photosensitive to light incident upon the backside of the sensor die. For BSI image sensors, the majority of photon absorption occurs near the backside silicon surface. To separate the electron-hole pairs created by photon absorption and drive the electrons to PD region 105, an electric field near the back silicon surface is helpful. This electric field may be created by doping the back surface and laser annealing. Laser annealing is an annealing process which creates localized heating.
For a thick P− epi layer 110, the laser pulse raises the back surface temperature greatly (e.g., in excess of 1000 C), but due to the short pulse, the temperature decreases quickly into the bulk of epi layer 110. However, when epi layer 110 is thin (e.g., P− epi layer 110<4 um thick), the insulation from inter-layer dielectric layer 120 and the remainder of the back-end-of-the-line (“BEOL”) elements may cause a significant increase in substrate and epitaxial layer temperature during laser annealing that can result in deleterious effects, such as dopant diffusion at temperatures greater than 800 C and/or BEOL metal deterioration/melting at temperatures greater than 400 C.
This problem may be solved by using a thicker final P− epi layer 110, which can be produced by removing less of the epi layer during the backside thinning process. Retaining a thick layer of silicon between the backside and the front side places the laser-irradiated high temperature back surface further away from the dopant profiles and metal/silicide contacts on the front side. However, increasing this thickness results in increased electrical crosstalk between adjacent pixels in an imaging sensor array. Therefore, the trend has been to make P− epi layer 110 thinner.